Optical Networks On Chip – Enabling Future Memory

Time: Wednesday, October 24th, 17:10
Speaker: Martijn HECK, Aarhus

Photonics has been the technology of choice for long-distance telecommunications for many decades. The key enablers here are the vast bandwidth of optical fibers and their low loss of, currently, below 0.2 dB/km. The loss of an optical fiber or waveguide is independent of the bandwidth of the optical signal. This is unlike electrical cables, like copper, where the losses tend to increase rapidly with increasing bandwidth, to multiple dBs per meter at 25‑GHz bandwidths. This means that there is a clear trade-off for interconnects: the higher the bandwidth, the shorter the length becomes where optical communications is the preferable solution.
Following this trend, in high-end datacenters, vertical-cavity-laser-based multimode fiber interconnects connect the servers, with silicon-photonic-based single-mode fiber interconnects as the highest bandwidth solutions, operating at 100/200 Gbps [1]. For on-board interconnects, i.e., between processors, memory and the edge of the server, new standards are currently being drawn up for so-called optical engines, making this a near-term reality [2]. And finally, pioneering work has shown that the optics can even be brought onto the processor, into an existing CMOS process, for the highest-bandwidth communications [3]. This technology is currently being commercialized [4].
Looking even further, optical networks-on-chip are being considered, albeit mostly theoretical. Initial design studies have shown the validity of replacing copper interconnects on the processor with an optical network, e.g., to connect cores in a multi-core processor [5,6]. Such approaches are based on energy-efficient silicon photonics, promising attojoule-per-bit communications [7].
Leveraging these technology developments and trends, in the H2020-funded project SPICE, we intend to push the boundaries even further, by trying to address single memory elements optically, e.g., to write magnetic tunnel junctions that have magneto-optic layers [8]. This eventually requires ultra-dense and ultra-low power networks, for overall memory energy consumption in the sub-20-fJ/bit range. I will present the opportunities for this technology.

This project has received funding from the European Union’s Horizon 2020 research
and innovation programme under grant agreement No 713481.

  1. Mekis et al., "A grating-coupler-enabled CMOS photonics platform." IEEE Journal of Selected Topics in Quantum Electronics 17, no. 3 (2011): 597-608.
  2. https://onboardoptics.org/, checked d.d. 11-10-2018
  3. Sun et al., "Single-chip microprocessor that communicates directly using light." Nature 528, no. 7583 (2015): 534.
  4. https://ayarlabs.com/, checked d.d. 11-10-2018
  5. Batten et al., "Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics." IEEE Micro 29, no. 4 (2009).
  6. J. R. Heck, and J. E. Bowers, "Energy efficient and energy proportional optical interconnects for multi-core processors: Driving the need for on-chip sources." IEEE Journal of Selected Topics in Quantum Electronics 20, no. 4 (2014): 332-343.
  7. A. B. Miller, "Attojoule optoelectronics for low-energy information processing and communications." Journal of Lightwave Technology 35, no. 3 (2017): 346-396.
  8. http://spice-fetopen.eu/, checked d.d. 11-10-2018